One of the main recent trends in the fabrication of ultra-large scale-integration (ULSI) circuits is the vertical stacking, or integration, of metal wiring circuits to form multilevel interconnection. Multilevel fabrication process has become an efficient way to increase circuit performance and increase the functional complexity of the circuits. One drawback of multilevel interconnection is the loss of topological planarity resulting from various photolithographic and etching processes. The various integrated circuit fabrication processes invariably produce nonplanar surface, or nonplanar topography, on the wafer, from which semiconductor devices are fabricated. During the multilevel metallization of VLSI or ULSI devices, the multiplicity of layers of nonplanar surfaces further add together to produce very serious topography problems. For example, the conductive or insulative properties of the various deposited films can be degraded on the area of the film layers across the step height. Those films in high topography areas can be easily broken during heat, electrical current, or mechanical stress steps, resulting in the pattern areas becoming discontinuous. Such discontinuity can cause the device to fail to perform its intended function. Furthermore, a nonplanar surface cannot be precisely focused during the photolithography process, because the depth of focus of the conventional photolithographic stepper will be deviated by different step heights of the wafer. Such an out-of-focus problem is more profound with device features of very small sizes.
To alleviate these problems, the wafer is planarized at various stages in the fabrication process to minimize non-planar topography and thus its adverse effects. Such planarization is typically implemented in the dielectric layers. However, it is possible to implement the planarization process in the conductor layer. One of the commonly used planarization processes is an SOG (spin-on-glass) process. More recently, chemical-mechanical polishing (CMP) processes have become very well received to planarize the wafer surface in preparation for further device fabrication. The CMP process mainly involves the step of holding a semiconductor wafer against a rotating polishing pad surface wetted by a polishing slurry, which typically comprises an acidic or basic etching solution in combination with alumina or silica particles. On the one hand, the liquid portion of the slurry chemically removes, loosens, or modifies the composition of the material on the wafer which is to be removed. On the other hand, the particle portion of the slurry, in combination of the rotating polishing pad, physically removes the chemical modified material from the wafer. Thus, the name "chemical-mechanical polishing" was obtained.
One of the sacrificial materials in the ULSI processes is a solution-type silicon dioxide, which is commonly referred to as the spin-on-glass (SOG). SOG is initially formed as a low viscosity solution which can be coated onto the nonplanar surface to quickly fill the recessed areas by a conventional spin coating technique. After the SOG coating, the coated layer is hard-baked to remove the solvent contained therein and turn the SOG layer into a hardened layer. Because of its high electrical resistance, the solidified SOG layer on top of the integrated circuit structure (i.e., the metal layer) must be etched back, conventionally by a dry (plasma) etch process involving fluoride gas in the reactive plasma chamber. If the SOG layer on the top surface of the wafer is not completely removed, it can generate the so-called vias poisoning, causing the vias to have a very high electrical resistance and adversely affect the interlayer conduction.
Conventional silicon oxide based SOG material have exhibited several disadvantages if they are used in CMP process. Polymer-based SOG materials offer many advantages. However, the polymer-based sacrificial material is not considered as a CMP sacrificial material because it exhibits a very low CMP removal rate using CMP slurries designed for conventional oxides. Thus, the IC manufacturers must stock two different types of chemical-mechanical polishing slurries. And the use of a different chemical-mechanical polishing slurry may cause material compatibility problems and other handling concerns.